1981 Intel Bubble memory component data catalog

The following information is from the Intel 1981 Component Data Catalog page 3-6 and 3-7.
Note that this is "Preliminary" info :-).

I skipped the BLOCK DIAGRAM, PIN CONFIGURATION, PACKAGE OUTLINE, SOCKET OUTLINE, PIN DESCRIPTION and the boring ABSOLUTE MAXIMUM RATINGS, D.C. AND OPERATING CHARACTERISTICS, DRIVE REQUIREMENTS and CONTROL PULSE REQUIREMENTS


  • 1,048,576 Bits of Usable Data Storage
  • Non-Volatile, Solid-Stale Memory
  • True Binary Organisation - 512 Bit
    Page and 2048 Pages
  • Major Track - Minor Loop Architecture
  • Redundant Loops with On-Chip Loop
    Map and Index
  • Block Replicate for Read; Block
    Swap for Write
  • Single Chip 20-Pin Dual In-Line
    Leadless Package and Socket
  • Small Physical Volume
  • Low Power per Bit
  • Maximum Data Rate 100 Kbit/sec

The Intel Magnetics 7110 is a very high density 1 megabit non-volatile, solid-state memory utilizing the magnetic bubble technology. The usable data storage capacity is 1,048,576 bits. The defect tolerant design incorporates redundant storage loops. The gross capacity of Intel Magnetics bubble memory is 1,310,720 bits.

The 7110 has a true binary organization to simplify system design, interfacing, and system software. The device is organized as 256 data storage loops each having 4096 storage bits. When used with Intel Magnetics complete family of support electronics the resultant minimum system is configured as 128K bytes of usable data storage. The support circuits also provide automatic error correction and transparent handling of redundant loops.

The 7110 has a major track-minor loop architecture; It has separate read and write tracks. Logically, the data is organized as a 512 bit page with a total of 2048 pages. The redundant loop information is stored on-chip in the bootstrap loop along with an index address code. When power is disconnected, the 7110 retains the data stored and the bubble memory system is restarted when power is restored via the support electronics under software control.

The 7110 is packaged in a dual in-line leadless package complete with permanent magnets and coils for the in-plane rotating field. In addition, the 7110 has a magnetic shield surrounding the bubble memory chip to protect the data from externally induced magnetic fields. The 7110 operating data rate is 100 Kbit/sec. The 7110 can be operated asynchronously and has start/stop capability.

GENERAL FUNCTIONAL DESCRIPTION


The Intel Magnetics 7110 is a 1 megabit bubble memory module organized as two identical 512K binary half sections. See Major Track-Minor Loop architecture diagram. Each half section is in turn organized as two 256K subsections referred to as quads.

The module consists of a bubble die mounted in a substrate that accommodates two orthogonal drive coils that surround the die. The drive coils produce a rotating magnetic field in the plane of the die when they are excited by 90º phase shifted triangular current waveforms. The rotating in-plane field is responsible for bubble propagation. One drive field rotation propagates all bubbles in the device one storage location (or cycle). The die-substrate-coil sub-assembly is enclosed in a package consisting of permanent magnets and a shield. The shield serves as a flux return path for the permanent magnets in addition to isolating the device from stray magnetic fields. The permanent magnets produce a bias field that is nearly perpendicular to the plane of the die. This field supports the existence of the bubble domains.

The package is constructed to maintain a 2.5 degree tilt between the plane of the bias magnet faces and the plane of the die. This serves to introduce a small component of the bias field into the plane of the die. During operation when the drive coils are energized this small in-plane component is negligible. During standby or when power is removed the small inplane field ensures that the bubbles will be confined to their appropriate storage locations. The direction of the in-plane field introduced by the package tilt (holding field) is coincident with the 0o phase direction of the drive field.

Quad Architecture

A 7110 quad sub-section is composed of the following elements shown on the architecture diagram.

  1. Storage Loops
    Eighty identical 4096 bit storage loops provide a total maximum capacity of 327,680 bits. The excess storage is provided for two purposes: a) it allows a redundancy scheme to increase device yield; and b) it provides the extra storage required to implement error correction.
  2. Replicating Generator (GEN)
    The generator operates by replicating a seed bubble that is always present at the generator site, (GEN).
  3. Input Track and Swap Gate
    Bubbles following generation are propagated down an input track. Bubbles are transferred to/from the input track from/to the 80 storage loops via series connected swap gates spaced every four propagation cycles along the track. The swap gate’s ability to transfer bubbles in both directions during an operation eliminates the overhead associated with removing old data from the loops before new data can be written. The swap gate is designed to function such that the logical storage loop position occupied by the bubble transferred out of each loop is filled by the bubble being transferred, into each loop. Transferred out bubbles propagate down the remaining portion of the input track where they are dumped into a bubble bucket guard rail.
  4. Output Track and Replicate Gate
    Bubbles are read out of the storage loops in a non-destructive fashion via a set of replicate gates. The bubble is split in two. The leading bubble is retained in the storage loop and the trailing bubble is transferred onto the output track. Replicate gates are spaced every four propagation cycles along the output track.
  5. Detector
    Bubbles, following replication, are propagated along the output track to a detector that operates on the magneto-resistance principle. The cylindrical bubble domains are stretched into long strip domains by a chevron expander and are then propagated to the active portion of the detector. The detector consists of a stack of interconnected chevrons through which a current is passed. As the strip domain propagates through the stack, its magnetic flux causes a fractional change in stack resistance which produces an output signal on the order of a few millivolts. The strip domain following detection is propagated to a bubble bucket guard rail. A “dummy” detector stack sits in the immediate vicinity. It Is connected in series with the active deflector and serves to cancel common mode pickup which originates predominately from the in-plane drive field.
  6. Boot Loop, Boot Swap, and Boot Replicate
    One of the two quads in each half chip contains a functionally active Boot Storage Loop. This loop is used to store:
    1. A loop mask code that defines which loops within the main storage area should be accessed. Faulty loops are “masked out” by the support electronics.
    2. A synchronization code that assigns data ad dresses (pages) to the data in the storage loops. Since bubbles move from one storage location to the next every field rotation, the actual physical location of a page of data is determined by the number of field rotations that have elapsed with respect to a reference.

The boot loop is read from and written into via the same input and output tracks as the main storage loops. However, it has independently accessed swap and replicate gates. The boot swap, under normal circumstances, is intended only to be used during basic initialization at the factory at which time loop mask and synchronization codes are written. The boot replicate is intended to be accessed every time power is applied to the bubble module and its peripheral control electronics. At such a time, the control electronics would read and store the mask information, plus utilize the synchronization information to establish the location of the data circulating within the loops.


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